The present invention relates generally to input buffers and more particularly to an input buffer capable of providing three unambiguous logic output states.
It is frequently necessary for one input of an integrated circuit to have the capability of forcing the circuit to more than two logic states. In CMOS PROM, for example, the address inputs are used as conventional addresses (namely, ones and zeros) and also to enable the circuitry for testing and decoding. To provide the multilevel logic states in bipolar PROMS, zener diodes are used in the input buffers. The use of zener diodes in FET integrated circuits has been found not to be advantageous since the control of the zener breakdown voltages would add extra processing complexity to the FET process. Also, with the use of zener diodes, the input voltages applied are limited to one polarity and, for normal operation, cannot exceed the zener breakdown voltage. In practice, this would limit the input swing on an FET circuit to about zero to seven volts.
Thus there exists a need for a buffer having a single input capable of handling positive and negative polarity input signals to provide at least three unambiguous logic output states and which is capable of handling reference voltage sources from four to eleven volts in normal operation.